Friday, October 14, 2011

Three VHDL Rules

Follow these rules INSIDE the process block.



1 -   Include all read signals/variables in the sensitivity list
 "Read signals" include all signals on the right hand side of <= and all signals used in comparisons.
2 -   Cover output assignments for ALL cases.
Can be done by assigning default output values before implementing logic.
3 -   Output signals can be assigned multiple times but only the last assignment holds.

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