CPU, RISC/CISC, Design, Pipelining

CPU

• Central Processing Unit
• ALU
• Registers
• Control Unit
• Datapath = ALU + registers + buses
• Program Counter (PC) -- bookmarks place in programs
• Instruction Register (IR) -- saves current instruction

RISC vs. CISC

Reduced Instruction Set

• simpler and shorter instructions
• doesn't rely on interpreter
• Ex: may take 5 instructions to complete what CISC does in one
• (RISC faster overall though because individual instructions faster - no interp)

Design Principles

• Do it on the Hardware 
• (faster)
• Only Load and Store should access memory 
• (so other things can be done in //)
• Give em' lots of registers
• (less memory calls)
• Instructions should be easy to decode
• (consistent length, format, etc.)
• Maximize Rate at which instructions are issued

Pipelining

• Task broken into stages
• EX: read, decode, fetch operation, execute, write
• Each stage completes its task for one item, moves to the next
• Basically like an assembly line
• Latency = amount of time to execute an instruction
• T = time / pipeline stage
• n  = # stages
• Latency = Tn
• Processor Bandwidth = MIPS a processor can execute
• MIPS = Millions of instructions per second