ECE 337 - Lab 1

Simple ALU:

Open XILINX ISE DESIGN SUITE.

Paste given code:

 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_alu is
port(
   ctrl: in std_logic_vector(2 downto 0);
   src0, src1: in std_logic_vector(7 downto 0);
   result: out std_logic_vector(7 downto 0)
   );
end simple_alu;

architecture cond_arch of simple_alu is
signal sum, diff, inc: std_logic_vector(7 downto 0);
begin
-- note conversion to signed and back to std_logic
inc <= std_logic_vector(signed(src0)+1);
sum <= std_logic_vector(signed(src0)+signed(src1));
diff <= std_logic_vector(signed(src0)-signed(src1));
result <= inc when ctrl(2)= '0' else
sum when ctrl(1 downto 0)= "00" else
diff when ctrl(1 downto 0)= "01" else
src0 and src1 when ctrl(1 downto 0)= "10"
else src0 or src1;
end cond_arch;
Select Design tab on side bar.
Select "simple_alu - cond_arch..." .vhd file in Hierarchy window on side bar.
In Processes window on sidebar, double-click Synthesize.
Double click View RTL Schematic.

Select second option (not wizard).
File -> Print Preview

Print preview gives a nicer schematic, but here are screenshots of the actual schematic:

And that's lab 1!