Input/Output Basic

BUSES

• DMA
• cycle stealing
• ISA
• PCI / EPCI

TERMINALS

• Two parts: Keyboard and Monitor

KEYBOARDS

• Keyboard Interrupt handler

CRT MONITORS

• Raster Scan

FLAT PANEL DISPLAYS

• LCD

VIDEO RAM

• Special memory on display's controller card
• used when refreshing displays (one value per pixel)

MICE


PRINTERS


MONOCHROME

COLOR

Secondary Memory

MEMORY HIERARCHIES
     As you go down the list, access time increases and price decreases.

1. CPU Registers
2. Cache
3. Main Memory
4. Magnetic Disk
5. Tape / Optical Disk

DISKS

• MAGNETIC
• FLOPPY
• IDE
• SCSI

RAID

CD-ROMS

• RECORDABLES
• REWRITABLES

DVDS

• "Digital (Video/Versatile) Disk"
• Uses Red Laser
• Smaller Pits than CDs
• Tighter spiral than CDs
• 4.7 GB for single side, single layer
• Dual Layer - reflective + semi-reflective layer
• Focus laser for different content
• 1.4 MB/sec... meh...
• Hollywood --> incompatible US and EUR DVDS 
• Can't buy and watch new movie before it has come out

BLU-RAYS

• Blue Laser (not Red like DVD)
• Shorter Wavelength
• Focuses Easier
• Allows for more Pits and Lands
• Stores up to 25 GIGABYTES on ONE SIDE!!
• Data Rate 4.5 MB/sec 
• Magnetic disk has better rate (100 MB/sec)

Cache Memory, Memory Packaging and Types

CACHE MEMORY

• From French word cacher meaning "to hide"
• Locality principle - When you refer to memory in short intervals, things you need are in the same general area.
• Chunks from slow main memory (Cache Lines) --> Cache (for later)
•  Mean Access Time 
• c = cache access time
• m = memory access time
• h = hit ratio = #times used variable (from Cache) / # times used variable (total)
• Mean Access Time = c + ( 1 - h ) m
• Unified vs. Split Cache
• Unified holds both data AND instructions
• Split --> 1 Cache each 
• allows for parallel access

MEMORY PACKAGING AND TYPES

• Memory Modules
• SIMM = Single Inline Memory Module
• DIMM = Dual Inline Memory Module
• SO-DIMM = Small Outline DIMM (just a smaller DIMM)
• Single or Double Sided ^
• 8 - 16 chips mounted on a board 
• typically about 32 MB/chip

Parallelism, Memory, Byte Ordering, Error Correcting

PARALLELISM

Instruction Level

• SuperScalar

Processor Level

• MultiProcessor
• CPUs share memory
• MultiComputers
• CPUs have own local memories

MEMORY

• Binary Coded Decimal (BCD) vs. Binary
• BCD translates each digit to binary individually
• Binary translates entire number  
• (more efficient - can express larger number than BCD with same # bits)

MEMORY ADDRESSES

• Memory - made up of cells (locations) that store information
• n Cells have addresses [0  --  n-1]
• Length of address depends on # of directly addressable cells in memory
• (independent of bits/cell)

BYTE ORDERING

• Big Endian (Most Significant cell gets index '0')
• Little Endian (Least gets '0')
• Jonathan Swift's Gulliver's Travels

ERROR CORRECTING CODE

• Codeword = m (data bits) + r (check bits) = n total bits
• ....
• ....
• Parity

Moore, Units, Virtual Machines

Intro Slides

• Moore's Law - annual 60% increase in number of transistors on a chip
• Virtual Machines written in some language Ln
• Ln is translated into L(n-1) of the next lowest machine
• repeat until actual computer is reached
•  Languages go from: 
• Problem Oriented -->Assembly-->Operating System-->Instruction Set Architecture -->MicroArchitecture-->Digital Logic (actual Hardware)
• Units....
• Nano and Giga   ==== 9
• Milli and Kilo    ==== 3
• Pico and Terra    === 12
• Micro and Mega ==== 6

CPU, RISC/CISC, Design, Pipelining

CPU

• Central Processing Unit
• ALU
• Registers
• Control Unit
• Datapath = ALU + registers + buses
• Program Counter (PC) -- bookmarks place in programs
• Instruction Register (IR) -- saves current instruction

RISC vs. CISC

Reduced Instruction Set

• simpler and shorter instructions
• doesn't rely on interpreter
• Ex: may take 5 instructions to complete what CISC does in one
• (RISC faster overall though because individual instructions faster - no interp)

Design Principles

• Do it on the Hardware 
• (faster)
• Only Load and Store should access memory 
• (so other things can be done in //)
• Give em' lots of registers
• (less memory calls)
• Instructions should be easy to decode
• (consistent length, format, etc.)
• Maximize Rate at which instructions are issued

Pipelining

• Task broken into stages
• EX: read, decode, fetch operation, execute, write
• Each stage completes its task for one item, moves to the next
• Basically like an assembly line
• Latency = amount of time to execute an instruction
• T = time / pipeline stage
• n  = # stages
• Latency = Tn
• Processor Bandwidth = MIPS a processor can execute
• MIPS = Millions of instructions per second

Three VHDL Rules

Follow these rules INSIDE the process block.



1 -   Include all read signals/variables in the sensitivity list

 "Read signals" include all signals on the right hand side of <= and all signals used in comparisons.

2 -   Cover output assignments for ALL cases.

Can be done by assigning default output values before implementing logic.

3 -   Output signals can be assigned multiple times but only the last assignment holds.

Concurrent Signal Assignments

Both Conditional and Selected signal assignments are forms of Concurrent Signal Assignements (in which changes are performed concurrently to other active statements.)

They can be assigned inside a process or architecture block.


Conditional Signal Assignment : Priority


Conditional signal assignment is similar to if-then-else.

A conditional signal assignment consists of an assignment to one output (or a collection of outputs, such as an array of any type) and a series of conditional when statements, as shown. To ensure that all conditions are covered, you can use a terminating when others clause.

architecture mux1 of my_mux is
begin
    Y <= A when Sel = "00" else
             B when Sel = "01" else
             C when Sel = "10" else
             D when others;
end mux1;

Selected Signal AssignmentA selected signal assignment is similar to a conditional signal assignment but differs in that the input conditions specified have no implied priority.
The "else" is the difference. These are bad examples because the code does not depend on the type of signal assignment. Either would work in this case.

begin
    with Sel select
        Y <= A when "00",
             B when "01",
             C when ?0",
             D when others;
end mux1;

From here.

ECE 337 - Lab 1

Simple ALU:

Open XILINX ISE DESIGN SUITE.

Paste given code:

 library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity simple_alu is
port(
   ctrl: in std_logic_vector(2 downto 0);
   src0, src1: in std_logic_vector(7 downto 0);
   result: out std_logic_vector(7 downto 0)
   );
end simple_alu;

architecture cond_arch of simple_alu is
signal sum, diff, inc: std_logic_vector(7 downto 0);
begin
-- note conversion to signed and back to std_logic
inc <= std_logic_vector(signed(src0)+1);
sum <= std_logic_vector(signed(src0)+signed(src1));
diff <= std_logic_vector(signed(src0)-signed(src1));
result <= inc when ctrl(2)= '0' else
sum when ctrl(1 downto 0)= "00" else
diff when ctrl(1 downto 0)= "01" else
src0 and src1 when ctrl(1 downto 0)= "10"
else src0 or src1;
end cond_arch;
Select Design tab on side bar.
Select "simple_alu - cond_arch..." .vhd file in Hierarchy window on side bar.
In Processes window on sidebar, double-click Synthesize.
Double click View RTL Schematic.

Select second option (not wizard).
File -> Print Preview

Print preview gives a nicer schematic, but here are screenshots of the actual schematic:

And that's lab 1!